| 000 | nam a22 a 4500 | ||
|---|---|---|---|
| 999 |
_c15883 _d15883 |
||
| 001 | BD-DhNSU-15883 | ||
| 003 | BD-DhNSU | ||
| 005 | 20190403061218.0 | ||
| 008 | 190403s2003 nyua|||g |||| 001 0|eng d | ||
| 010 | _a | ||
| 020 | _a1402074018 | ||
| 040 |
_aDLC _cDLC _dBD-DhNSU |
||
| 041 | _aeng | ||
| 050 | 0 | 0 |
_aTK7885.7 _b.B47 2003 |
| 082 | 0 | 0 |
_a621.3815 _bB496w |
| 100 | 1 | _aBergeron, Janick | |
| 245 | 0 | 0 |
_aWriting testbenches : _bfunctional verification of HDL models / _cJanick Bergeron |
| 250 | _a2nd ed. | ||
| 260 |
_aNew York : _bSpringer, _cc2003. |
||
| 300 |
_axxix, 475 p. : _bill. ; _c25 cm. |
||
| 650 | 0 | _aComputer hardware description languages Integrated circuits | |
| 650 | 0 | _aVerification | |
| 942 |
_2lcc _cBK |
||